1. Field of the Invention
The invention relates generally to a semiconductor technology, and more particularly to, a method of manufacturing a MOSFET of an elevated source/drain structure.
2. Description of the Prior Art
In order to improve the properties of a semiconductor device, a shallow source/drain junction is required. As the source/drain junction becomes shallower, however, there occurs a problem that a junction resistance is increased. In order to solve this problem, an elevated source/drain structure has been proposed.
Referring now to FIGS. 1A to 1E, a method of manufacturing a conventional MOSFET of an elevated source/drain structure will be explained.
In a method of manufacturing a conventional MOSFET of an elevated source/drain structure, a device separation film 11 is formed on a silicon substrate 10, and a gate oxide film 12, a conductive film for gate electrode 13 and a mask insulating film 14 are sequentially formed and are then patterned to form a gate, as shown in FIG. 1A.
Next, a sidewall spacer 15 is formed at the sidewall of the gate using an oxide film or a nitride film, as shown in FIG. 1B.
Then, an epitaxial silicon layer 16 is selectively formed on the exposed silicon substrate 10 by chemical vapor deposition (CVD) method, as shown in FIG. 1C.
Thereafter, impurity ion implantation is implemented for forming a source/a drain at the epitaxial silicon layer 16, as shown in FIG. 1D.
Next, annealing process for activating ions-implanted dopants is performed, as shown in FIG. 1E. Thus, the dopants are diffused into the silicon substrate 10 by a certain depth, thus forming a MOSFET of an elevated source/drain structure.
As mentioned above, conventionally, after the epitaxial silicon layer 16 of about 1000 xc3x85 is grown, a source/drain junction is formed by ion implantation and annealing process.
However, when the epitaxial silicon layer 16 is grown, the edge portion of the epitaxial silicon layer 16, that is, a facet region A is formed at {311} or {111} orientation plane.
Therefore, after diffusion process, the distribution of the dopants has a pocket shape B. This shape of dopant distribution obstructs prevention of short channel effect that is obtained by implementing a uniform and shallow junction being the greatest advantage in an elevated source/drain structure. Rather than, it causes a drain-induced barrier-lowering (DIBL) phenomenon by which electric filed generated at the drain region affects the source region and thus significantly degrades electric characteristic around the gate.
FIG. 2 is a photograph taken by a scanning electronic microscope (SEM) for explaining that a facet region is generated after an epitaxial silicon layer is grown.
As one solution to solve the above-mentioned problems, there has been proposed a method by which a secondary spacer is applied to improve a facet region, as shown in FIG. 3.
In concrete, a device separation film 31 is formed on a silicon substrate 30, and a gate oxide film 32, a conductive film for gate electrode 33 and a mask insulating film 34 are sequentially formed and are then patterned to form a gate.
Next, a first sidewall spacer 35 is formed at the sidewall of the gate using an oxide film or a nitride film. Then, an epitaxial silicon layer 36 is selectively grown on the exposed silicon substrate 30.
Thereafter, a second sidewall spacer 37 is formed using the nitride film or the oxide film. At this time, the second sidewall spacer 37 is formed to have a similar thickness to the width of the facet region, enough to cover the facet region generated at a portion neighboring to the first sidewall spacer 35.
Then, after impurity ion implantation is implemented for forming a source/a drain at the epitaxial silicon layer 36, annealing process for activating ions-implanted dopants is performed. Thus, the dopants are diffused into the silicon substrate 10 by a certain depth, thus forming a MOSFET of an elevated source/drain structure.
Though this method solves the problem that the distribution of dopants has a pocket shape, however, formation of the junction region around the gate is severely prohibited due to the second sidewall spacer 37, thus causing increased channel length. Therefore, there is a problem that it degrades the performance of a device in view of drain saturation current Idsat and trans-conductance (gm). Also, there is a problem that the total number of process is increased due to additional process for forming the second sidewall spacer 37 and the manufacture cost of a device is thus increased.
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing a fact profile generated at the time when an epitaxial silicon layer is formed.
In order to accomplish the above object, a method of manufacturing a semiconductor device according to the present invention is characterized in that it comprises a first step of forming a gate including a mask insulating film and a sidewall spacer insulating film on a silicon substrate; a second step of growing a first epitaxial silicon layer on the exposed silicon substrate; and a third step of selectively growing a second epitaxial silicon layer on a facet region, wherein a boundary layer (layer in which the flow of hydrogen gas is substantially 0) for the flow of hydrogen gas on the entire structure for which the second step is completed and wherein the temperature of the facet region formed at the edge portion on the gate side in the first epitaxial silicon layer is higher than the temperature of its neighboring first epitaxial silicon layer.
Preferably, a method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a gate including a mask insulating film and a sidewall spacer insulating film on a silicon substrate; a second step of growing a first epitaxial silicon layer on the exposed silicon substrate; a third step of forming a thin oxide film along the surface of the first epitaxial silicon layer; and a four step of selectively growing a second epitaxial silicon layer on a region in which the oxide film is removed, while selectively removing the oxide film in the facet region, wherein a boundary layer (layer in which the flow of hydrogen gas is substantially 0) for the flow of hydrogen gas on the entire structure for which the third step is completed and wherein the temperature of the oxide film in the facet region formed at the edge portion on the gate side in the first epitaxial silicon layer is higher than the temperature of its neighboring oxide film.
Also, a method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a gate including a mask insulating film and a sidewall spacer insulating film on a silicon substrate; a second step of growing a first epitaxial silicon layer on the exposed silicon substrate; a third step of forming a thin oxide film along the surface of the first epitaxial silicon layer; a fourth step of implementing hydrogen bake at the temperature of 750xcx9c850xc2x0 C. to selectively remove the oxide film on the facet region formed at the edge portion on the gate of the first epitaxial silicon layer; and a fifth step of selectively growing a second epitaxial silicon layer on a region in which the oxide film is removed.